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HTG13J0 4-Bit Microcontroller
Features
* * * * * * * * *
Operating voltage: 2.4V~3.3V Eight input lines Three output lines Five working registers RC oscillator for system clock 8K8 program ROM 1604 data RAM 408 segment LCD driver, 1/5 bias, 1/8 duty 8-bit programmable timer with built-in frequency source
* * * * * * * *
Internal timer overflow interrupt 16 kinds of programmable sound effect One-level subroutine nesting Halt function and wake up feature reduce power consumption Halt instruction 8-bit table read instruction Up to 4.0msec instruction cycle (1.0MHz system clock), at VDD=3V 96 powerful instructions
General Description
The HTG13J0 is a processor from Holtek s 4-bit stand alone single chip microcontroller specially designed for LCD product applications. It is especially suited for applications requiring low power consumption system with many LCD segments, such as calculator, scale, subsystem controller, hand-held LCD products and electronic appliances.
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Block Diagram
S ta c k OSCI
T im e r ALU PA0 PA1 PA2
PA OSCO PC ACC PA3
RES TEST1 TEST2 T1D In s tr u c tio n D ecoder C o n tro l and T im in g C ir c u it PP ROM R0 R1 R2 R3 R4 Sound E ffe c t T e m p o ra ry D a ta R A M D is p la y D a ta RAM PS
PP0 PP1 PP2 PP3 PS0 PS1 PS2 PS3
VDD VSS
BZ BZ
LCD
D r iv e r
SEG 38
SEG 39
COM0
COM1
COM7
SEG0
SEG1
SEG2
Notes: ACC: Accumulator R0~R4: Working registers PP, PS: Input ports
PC: Program counter PA0~PA2: Output port PA3: ROM bank switch
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Pad Assignment
SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG0
1 52 BZ VDD OSCI 2 3 4 51 50 49 48 47 OSCO T512 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 TEST1 TEST2 PS2 PS1 PS0 VSS 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 (0,0) 46 45 44 43 42 41 40 39 38 37 36 35 34 26 27 28 29 30 31 32 33 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36
70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 BZ
* The IC substrate should be connected to VSS in the PCB layout artwork.
SEG1 T1D
SEG2
Chip size: 2746 3552 (mm)
SEG3
SEG4 PA2
SEG5
SEG6 PA1
SEG7
SEG8
SEG9 PP0
SEG38
SEG39
RES
SEG37
PP2
PP3
PP1
PS3
PA0
2
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Pad Coordinates
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 X -1244.25 -1244.25 -1203.75 -1244.25 -1244.25 -1244.25 -1244.25 -1244.25 -1244.25 -1244.25 -1244.25 -1244.25 -1244.25 -1244.25 -1244.25 -1244.25 -1244.25 -1244.25 -1244.25 -1206.45 -923.85 -671.40 -469.35 -217.35 22.95 232.20 371.70 511.20 650.70 790.20 929.70 1069.20 1208.70 1244.25 1244.25 Y 1523.47 1256.62 1017.25 861.97 353.02 227.02 101.03 -24.98 -150.98 -276.98 -402.98 -528.97 -654.97 -780.97 -906.97 -1032.97 -1158.97 -1284.97 -1410.97 -1617.53 -1556.78 -1568.47 -1556.78 -1556.78 -1556.78 -1617.53 -1617.53 -1617.53 -1617.53 -1617.53 -1617.53 -1617.53 -1617.53 -1361.03 -1224.67 Pad No. 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 X 1244.25 1244.25 1244.25 1244.25 1244.25 1244.25 1244.25 1244.25 1244.25 1244.25 1244.25 1244.25 1244.25 1244.25 1244.25 1244.25 1244.25 1228.95 1084.95 954.45 823.95 693.45 562.95 432.45 301.95 171.45 40.95 -89.55 -220.05 -350.55 -481.05 -611.55 -742.05 -872.55 -1003.05 Unit: mm Y -1080.67 -936.67 -792.67 -648.67 -504.67 -360.67 -216.68 -72.68 71.32 215.32 359.33 503.33 729.22 882.22 1035.22 1188.22 1341.22 1617.53 1617.53 1617.53 1617.53 1617.53 1617.53 1617.53 1617.53 1617.53 1617.53 1617.53 1617.53 1617.53 1617.53 1617.53 1617.53 1617.53 1617.53
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Pad Description
Pad No. 1 2 3 4 5 6 15 16 21 7~14 17~19 22 20 23~25 Pad name BZ BZ VDD OSCI OSCO T512 TEST1 TEST2 T1D COM7~COM0 PS2~PS0 PS3 VSS PA2~PA0 I/O O I I O O I I O O I I O Mask Option * 3/4 3/4 Description Sound effect output Positive power supply OSCI, OSCO are connected to resistor for internal system clock. For test mode only TEST1 and TEST2 must be open when the chip is in normal operation (with internal pull high resistor). Output for LCD panel common plate 4-bit port for input only Negative power supply, GND 3-bit latch port for output only
3/4 3/4 Pull-high or None ** 3/4 CMOS or NMOS Open Drain Pull-high or None ** 3/4 3/4
26~29
PP0~PP3
I
4-bit port for input only Input to reset LSI Reset is active at logical low level. LCD driver outputs for LCD panel segment
30 31~70 *: **:
RES SEG39~SEG0
I O
6 internal sources deriving from system clock can be selected as sound effect clock by mask option. If Holtek s sound library is invoked, only 128K and 64K is accepted. Each bit of input ports PS, PP can be a trigger source of HALT interrupt. That can be specified by mask option.
Absolute Maximum Ratings
Supply Voltage .............................-0.3V to 5.5V Input Voltage ................VSS-0.3V to VDD+0.3V Storage Temperature ................-50C to 125C Operating Temperature ..................0C to 70C
Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum Ratings" may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
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D.C. Characteristics
Symbol VDD IDD ISTB VIL1 VIH1 VIL2 VIH2 IOL1 IOH1 IOL2 IOH2 IOL3 IOH3 IOL4 IOH4 RPH Parameter Operating Voltage Operating Current Standby Current Input Low Voltage PS, PP Input High Voltage PS, PP Input Low Voltage RES Input High Voltage RES Port A, BZ and BZ Output Sink Current Port A, BZ and BZ Output Source Current Segment 0~7 Output Sink Current Segment 0~7 Output Source Current Segment 8~39 Output Sink Current Segment 8~39 Output Source Current Common Sink Current Common Source Current Pull-high Resistance Test Conditions VDD 3/4 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V Conditions 3/4 No load, fSYS=500kHz System halt 3/4 3/4 3/4 3/4 VDD=3V, VOL=0.3V VDD=3V, VOH=2.7V VLCD=3V, VOL=0.3V VLCD=3V, VOH=2.7V VLCD=3V, VOL=0.3V VLCD=3V, VOH=2.7V VLCD=3V, VOL=0.3V VLCD=3V, VOH=2.7V PS, PP, RES Ta=25C Min. Typ. Max. Unit 2.4 3/4 3/4 0 2.1 0 2.6 1.5 -0.8 80 -50 40 -30 60 -60 50 3/4 200 3/4 3/4 3/4 3/4 3/4 3.0 -1.5 130 -90 80 -60 120 -120 3/4 3.3 500 1 0.6 3.0 0.6 3.0 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 300 V mA mA V V V V mA mA mA mA mA mA mA mA kW
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A.C. Characteristics
Symbol fSYS fLCD tCOM tCY tRES fSOUND Parameter System Clock LCD Clock LCD Common Period Cycle Time Reset Pulse Width Sound Effect Clock Test Conditions VDD 3V 3V 3/4 3/4 3/4 3/4 Conditions R:680kW~5kW 3/4 1/8 duty fSYS=1.0MHz 3/4 3/4 Min. 32 3/4 3/4 3/4 5 3/4 Typ. 3/4 512* (1/fLCD)8 4.0 3/4 64 or 128 ** Max. 1000 3/4 3/4 3/4 3/4 3/4 Ta=25C Unit kHz Hz Sec ms ms kHz
*: In general, fLCD is selected and optimized by Holtek according to fSYS and operating voltage. **: Only these two clock signal frequencies are supported by the Holtek sound library.
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Functional Description
Program counter - PC The bit 13 of program memory is controlled by PA3 which can change the address of the program. There are two banks of the program memory, which are selected by PA3, every bank is 4KB ROM. The instruction "UT PA,A" is used to change the value of PA3. Then, low or high 4K ROM is selected accordingly. All instructions are not effective on crossing bank, unless the value of PA3 is changed in advance. The 12-bit program counter (PC) controls the sequence in which the instructions stored in program ROM are executed and its contents specify a maximum of 4096 addresses. Program Counter Mode PA3 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 Initial reset Internal interrupt External interrupt Jump, call instruction Conditional branch 1 PA3 PA3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 PC2 0 1 0 PC2 PC2 S2 PC1 0 0 0 PC1 PC1 S1 PC0 0 0 0 PC0 PC0 S0 After accessing a memory word to fetch an instruction code, the contents of the program counter are incremented by 1 or 2, then the program counter will point to the memory word containing the next instruction code. When executing the jump instruction (JMP, JNZ, JC,JTMR...), subroutine call, internal interrupt, external interrupt or return from subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction.
PA3 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PA3 @ S11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 S10 S9 S8 S7 S6 S5 S4 S3
Return from PA3 subroutine
Program counter Notes: PC11~PC0: Instruction code bits S11~S0: Stack register bits @: PC11 keeps the current value PA3: Bank value bits
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Program memory - ROM The program memory is used to store program instruction which is to be executed. It is organized with 8192 8 bits and addressed by the program counter and PA3. Certain locations in bank 0 of the program memory are reserved for specific usage:
* Location 0004H * Location 1008H
Activating the PS or PP input pins of the processor with the interrupts enabled during HALT mode causes the program to jump to this location.
* Location 1n00H~1nFFH (n=current number)
This area are reserved for TIMER interrupt service program. A timer interrupt resulting from TIMER overflow, if interrupt is enabled the CPU begins execution at location 0004H.
* Location 0008H
Activating the PS or PP input pins of the processor with the interrupts enabled during HALT mode causes the program to jump to this location.
* Location 0n00H~0nFFH (n=current number)
and 1F00H~1FFFH. The last 256 bytes of each page in the program memory, addressed from 1n00H to 1nFFH and 1F00H to 1FFFH can be used as a loop up table. The instructions READ R4A, READ MR0A, READF R4A, READF MR0A can read the table and transfer the contents of the table to ACC and R4 or transfer to ACC and data memory addressed by register pair "R1,R0" These area may function as normal program memory depending on the requirement. Note that the page number n must be greater than zero, some locations in page 1 are reserved for specific usage as mentioned. The program memory (ROM) mapping is shown below:
0000H 0003H 0004H Timer interrupt subroutine of bank 0 0007H 0008H External interrupt subroutine of bank 0 000BH Page n look-up table (256 bytes) of bank 0 0F00H 0FFFH 1000H 1003H 1004H Timer interrupt subroutine of bank 1 1007H 1008H External interrupt subroutine of bank 1 100BH Page F look-up table (256 bytes) of bank 0 Program ROM Reset initial program
and 0F00H~0FFFH. The last 256 bytes of each page in the program memory, addressed from 0n00H to 0nFFH and 0F00H to 0FFFH can be used as a look up table. The instructions READ R4A, READ MR0A, READF R4A, READF MR0A can read the table and transfer the contents of the table to ACC and R4 or transfer to ACC and data memory addressed by register pair R1,R0 . These area may function as normal program memory depending on the requirement. Note that the page number n must be greater than zero, some locations in page 0 are reserved for specific usage as mentioned. Certain locations in bank 1 of the program memory are reserved for specific usage:
* Location 1000H
This area are reserved for the initialization program. After reset, the CPU always begins execution at location 1000H.
* Location 1004H
Page look-up table (256 bytes) of bank 1 1F00H Page F look-up table (256 bytes) of bank 1 1FFFH 8 bits
This area is reserved for TIMER interrupt service program. A timer interrupt resulting from TIMER overflow, if interrupt is enabled, the CPU begins execution at location 1004H.
Program memory
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In the execution of an instruction, the program counter is added before the executing phase. So a careful manipulation of READ MR0A and READ R4A is needed in the page margin. Stack register The stack register is a group of registers used to save the contents of the program counter (PC) and is arranged in 13 bits 1 level. One bit is used to store the carry flag. An interrupt will force the contents of the PC and the carry flag onto the stack register. A subroutine call will also cause the PC contents to be pushed onto the stack; however the carry flag will not be stored. At the end of a subroutine or an interrupt (indicated by a return instruction RET or RETI), the contents of the stack register are returned to the PC. Executing "RETI" instruction will restore the carry flag from the stack register, but "RET" does not. Working registers - R0,R1,R2,R3,R4 These five registers are usually used to store the frequently accessed data. The working register can be incremented (+1) or decremented (-1). The JNZ Rn, address (n=0,1,4) instruction makes efficient use of the working register as a program loop counter. Also the register pairs of R1, R0 and R3, R2 can be used as the data memory pointer, when the data memory transfer instruction is executed. Data memory - RAM The data memory is a static RAM organized with 256 4 bit format and is used to store temporary data and display data. All of the data memory locations are indirectly addressable through the register pair "R1,R0" or "R3,R2". There are two areas in the data memory, temporary data area and display data area. Access to the temporary data memory is made through 00H-9FH address, and access to the display data memory is made through B0H-FFH address. The locations between the temporary and display data areas are undefined and cannot be used.
00H A0H Undefined Area B0H FFH Display Data Area (80 x 4) 4 bits Data RAM Temporary Data Area (160 x 4)
Data memory
When data is written in the display area, the LCD driver automatically reads it and gene-rates an LCD driving signal. Accumulator - ACC The register ACC plays the most important role in data manipulation and data transfer. It is not only one of the sources of input to the ALU but also the destination of the result due to ALU. Data transfer can be performed between ACC and other registers, data memory or I/O ports. Arithmetic and logic unit - ALU This circuit performs arithmetic and logic operation. The ALU provides the following functions: Arithmetic operation (ADD, ADC, SUB, SBC, DAA)
* Logic operation (AND, OR, XOR) * Rotation (RL, RR, RLC, RRC) * Increment and Decrement (INC, DEC) * Branch decision (JZ, JNZ, JC, JNC...) * The ALU not only outputs the results of data
operation but also sets the status of carry flag (C) in some instructions. Timer This is a programmable 8-bit count-up counter internal frequency sources to aid the user in counting and generate accurate time base.
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The Timer is presettable and readable with software instructions. "TIMER XXH", "MOV TMRL,A" and "MOV TMRH,A" preload TIMER value. "MOV A,TMRL" and "MOV A,TMRH" read the contents of the TIMER to ACC. The Timer is stopped by a hardware reset or "TIMER OFF" instruction and started by a TIMER ON instruction. Once the Timer is started, it will increment to its maximum count (FFH) and overflow to zero (00H) and will not stop until there is a TIMER OFF instruction or reset. When an overflow occurs, it will set the Timer Flag (TF) simultaneously. If interrupt is enabled, the Timer circuit supports TF for internal interrupt. The state of the TF is also testable with conditional instruction JTMR. The Timer flag is cleared after the interrupt or JTMR instruction is executed. The frequency of internal frequency source can be selected by mask option. m = 2n Where n=0, 1, 2......13 except 6, by mask option (the sixth stage is reserved for internal use). Interrupt The HTG13J0 provide both internal and external interrupt modes. The DI and EI instructions are used to disable and enable the interrupts. During halt mode, if the PP or PS input pin is triggered on a high to low transition in the enable interrupt mode and the program is not within a CALL subroutine the external interrupt is activated. This causes a subroutine call to location 8 and resets the interrupt latch. Likewise when the timer flag is set in the enable interrupt mode and the program is not within a CALL subroutine, the internal interrupt is activated. This causes a subroutine call to location 4 and resets the timer flag. When running under a CALL subroutine or DI, the interrupt acknowledge is on hold until the RET or EI instruction is invoked. The CALL instruction should not be used within an interrupt routine as unpredictable result may occur. If within a CALL subroutine, an interrupt occurs, the interrupt will be serviced after leaving the CALL subroutine. The interrupts are disabled by a hardware reset or a DI instruction. They remain disabled until the EI instruction is executed. Each input port pin can be programmed by mask option to have an external interrupt function in the HALT mode. Initial reset The HTG13J0 provide a RES pin for system initialization. Since the RES pin has internal pull high resistor, only an external 0.1m~1m capacitor is needed. If the reset pulse is generated externally, it must be held low for at least 5 ms. When RES is active, the internal block will be initialized as follows: PA3 and PC TIMER Timer flag SOUND Interrupt BZ and BZ output Halt This is a special feature of HTG13J0. It will stop the chip s normal operation and reduce power consumption. When the instruction HALT is executed, then either of the following will occur:
* The system clock will be stopped * The contents of the on-chip RAM and regis-
1000H Stop Reset (low) Sound off and One sing mode Disabled High level
Output Port A high (or floating state)
ters remain unchanged
* LCD segments and commons keep VDD volt-
age (i.e. LCD becomes blank) The system can leave the HALT mode by ways of initial reset or external interrupt and wake-up from the following entry of the program counter value.
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Initial reset: 1000H. Interrupt (enabled): 1008H or 0008H. Interrupt (disabled): next address of HALT instruction. In HALT mode, each bit of ports PP, PS, can be used as external interrupt by mask option to wake-up the system. This signal is active in low-going transition. Sound effect HTG13J0 provides sound effect circuit which offers up to 16 sounds with 3 effects of tone, boom and noise. Holtek supports a sound library which have melody, alarm, machine gun shooting, etc. That can meet various requirements. Whenever the instruction "SOUND n" or "SOUND A" is executed, the specified sound begin playing. Whenever "SOUND OFF" is executed, it terminates the singing sound immediately. There are two singing mode, SONE mode and SLOOP mode, this is activated by "SOUND ONE" and "SOUND LOOP". In SONE mode, the sound that has been specified plays just once. In SLOOP mode, the sound being specified keeps playing repeatedly. Since sound 0~11 contain 32 notes, sound 12~15 contain 64 notes, the later possess better sound than the former. The frequency of sound effect circuit can be selected by mask option. m = 2m Where m=0, 1, 2, 3, 4, 5 The Holtek s sound library only supports sound clock frequency 128K or 64K. If it is desired to utilize Holtek s sound library, proper system clock and mask option should be selected. LCD display memory As mentioned in the data memory section, the LCD display memory is embedded in the data memory. It can be read and written to as normal data memory. The following figure shows the mapping between display memory and LCD pattern.
DISPLAY MEMORY FEH COM 0 1 2 3 FFH 4 5 6 7 FDH FBH F9H B5 B3 B1 0 1 2 3 FCH FAH F8H B4 B2 B0 BIT 0 1 2 3
SEGMENT
0
1
2
3
37
38
39
LCD display memory To turn on/off the display, the programmer just writes 1/0 to the corresponding bit of the display memory. The LCD display module may have any form as long as the number commons is no more than 8 and the segment is no more than 40. LCD driver output The output number of the LCD driver is 40 8. That can directly drive an LCD with 1/8 duty cycle and 1/5 bias. All LCD segments are random at the initial clear mode. The bias voltage circuit of the LCD display is built-in. No external resistor is needed. The LCD driving clock frequency shall be fixed in 512Hz. That can not be selected by the user, and Holtek will set it according to the application.
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An example of an LCD driving waveform (1/8 duty and 1/5 bias) is shown below.
64Hz 1 512Hz VDD 4/5 VDD COM0 3/5 VDD 2/5 VDD 1/5 VDD GND VDD 4/5 VDD COM1 3/5 VDD 2/5 VDD 1/5 VDD GND VDD 4/5 VDD 3/5 VDD 2/5 VDD 1/5 VDD GND 2 3 4 5 6 7 8 1 2 3 4 5
VDD
internal bus
D CK
Q Q
mask option
Output port - PA0~PA2 Output port PA0~PA2 A mask option is available to select whether the output is a CMOS or open drain NMOS type. After an initial clear, the output port PA defaults high for CMOS or floating for NMOS. Note: PA3 controls bit 13 of the program memory. Be careful about PA3. When instruction "OUT PA,A" is operated, port A is changed as well. Mask option The following options are available by mask option which must be selected prior to manufacturing.
* Each bit of input ports PS, PP with or without
SEG0
Oscillator circuit Only one external resistor is needed for HTG13J0 oscillator circuit. The system clock is also used as the reference signal of LCD driving clock, sound effect clock, and internal TIMER frequency source. One HTG13J0 machine cycle consists of a sequence of 4 states numbered T1 to T4. Each state lasts for one oscillator period. The machine cycle is 4ms, if the system frequency is up to 1.0MHz. Input ports PS, PP All ports can have internal pull high resistors
VDD
pull-high resistor.
* Each bit of input ports PS, PP function as
HALT interrupt trigger.
wake-up pull-high mask option wake-up mask option read control
* Each bit of output port PA0~PA2 with CMOS
or open drain NMOS.
* 8 bit programmable TIMER with internal fre-
internal bus
determined by mask option. Every bit of the input ports PP and PS can be specified to be a trigger source to wake up the HALT interrupt by mask option. A high to low transition on one of these pins will wake up the device from a HALT status.
quency sources. There are 13 (the sixth stage is reserved for internal use) internal frequency sources which can be selected as clocking signal.
* Six kinds of sound clock frequency:
fSYS/2 , m=0, 1, 2, 3, 4, 5
m
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Application Circuits
PA0 PA1 PA2 OUTPUT PORT
COM0 COM1 LC D COM7 (1 /5 P a tte rn B ia s , 1 /8 D u ty )
PP0 PP1 PP2 PP3 IN P U T PORT
SEGMENT OUTPUT
X 40
HTG 13J0
PS0 PS1 PS2 PS3 IN P U T PORT BZ BZ
R* OSCI OSCO
RES
0 . 1 F ~ 1 F
R*: depends on the required system clock frequency (R=680kW~5kW, at VDD=3V)
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Instruction Set Summary
Mnemonic Arithmetic ADD A,[R1R0] ADC A,[R1R0] SUB A,[R1R0] SBC A,[R1R0] ADD A,XH SUB A,XH DAA Logic Operation AND A,[R1R0] OR A,[R1R0] XOR A,[R1R0] AND [R1R0],A OR [R1R0],A XOR [R1R0],A AND A,XH OR A,XH XOR A,XH Increment and Decrement INC A INC Rn INC [R1R0] INC [R3R2] DEC A DEC Rn DEC [R1R0] DEC [R3R2] Data Move MOV A,Rn MOV Rn,A MOV A,[R1R0] MOV A,[R3R2] MOV [R1R0],A MOV [R3R2],A MOV A,XH MOV R1R0,XXH MOV R3R2,XXH MOV R4,XH Move register to ACC Move ACC to register Move data memory to ACC Move data memory to ACC Move ACC to data memory Move ACC to data memory Move immediate data to ACC Move immediate data to R1 and R0 Move immediate data to R3 and R2 Move immediate data to R4 1 1 1 1 1 1 1 2 2 2 1 1 1 1 1 1 1 2 2 2 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Increment ACC Increment register Increment data memory Increment data memory Decrement ACC Decrement register Decrement data memory Decrement data memory 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC 1 1 1 1 1 1 2 2 2 1 1 1 1 1 1 2 2 2 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Add data memory to ACC Add data memory with carry to ACC Subtract data memory from ACC Subtract data memory from ACC with borrow Add immediate data to ACC Subtract immediate data from ACC Decimal adjust ACC for addition 1 1 1 1 2 2 1 1 1 1 1 2 2 1
O O O O O O O
Description
Byte Cycle CF
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Mnemonic Rotate RL A RLC A RR A RRC A Input and Output IN A,Pi OUT PA,A Branch JMP addr JC addr JNC addr JTMR addr JAn addr JZ A,addr JNZ A,addr JNZ Rn,addr Subroutine CALL addr RET RETI Flag CLC STC EI DI NOP Timer TIMER XXH TIMER ON TIMER OFF MOV A,TMRL MOV A,TMRH MOV TMRL,A MOV TMRH,A Set 8 bits immediate data to TIMER Set TIMER start counting Set TIMER stop counting Move low nibble of TIMER to ACC Move high nibble of TIMER to ACC Move ACC to low nibble of TIMER Move ACC to high nibble of TIMER 2 1 1 1 1 1 1 2 1 1 1 1 1 1 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Clear carry flag Set carry flag Enable interrupt Disable interrupt No operation 1 1 1 1 1 1 1 1 1 1 0 1 3/4 3/4 3/4 Subroutine call Return from subroutine or interrupt Return from interrupt service routine 2 1 1 2 1 1 3/4 3/4 O Jump unconditional Jump on carry=1 Jump on carry=0 Jump on timer out Jump on ACC bit n=1, n=0,1,2,3 Jump on ACC is zero Jump on ACC is not zero Jump on register Rn not zero, n=0,1,4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Input port-i to ACC, port-i=PS,PP Output ACC to port-A 1 1 1 1 3/4 3/4 Rotate ACC left Rotate ACC left through the carry Rotate ACC right Rotate ACC right through the carry 1 1 1 1 1 1 1 1
O O O O
Description
Byte Cycle CF
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Mnemonic Table Read READ R4A READ MR0A READF R4A READF MR0A Sound Control SOUND n SOUND A SOUND ONE SOUND LOOP SOUND OFF Miscellaneous HALT Enter power down mode 2 2 3/4 Active SOUND channel n Active SOUND channel with Accumulator Turn on SOUND one mode Turn on SOUND repeat mode Turn off SOUND 2 1 1 1 1 2 1 1 1 1 3/4 3/4 3/4 3/4 3/4 Read ROM code of current page to R4 and ACC Read ROM code of current page to M(R1,R0),ACC Read ROM code of page F to R4 and ACC Read ROM code of page F to M(R1,R0),ACC 1 1 1 1 2 2 2 2 3/4 3/4 3/4 3/4 Description Byte Cycle CF
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HT13J0
Instruction Definitions
ADC A,[R1R0] Machine Code Description Operation ADD A,XH Machine Code Description Operation ADD A,[R1R0] Machine Code Description Operation AND A,XH Machine Code Description Operation AND A,[R1R0] Machine Code Description Operation AND [R1R0],A Machine Code Description Operation Add data memory contents and carry to accumulator 00001000 The contents of the data memory addressed by the register pair "R1,R0" and carry are added to the accumulator. Carry is affected. ACC ACC+M(R1,R0)+C Add immediate data to accumulator 01000000 ACC ACC+XH Add data memory contents to accumulator 00001001 The contents of the data memory addressed by the register pair R1,R0" is added to the accumulator. Carry is affected. ACC ACC+M(R1,R0) Logical AND immediate data to accumulator 01000010 0000dddd Data in the accumulator is logical AND with the immediate data specified by code. ACC ACC "AND" XH Logical AND accumulator with data memory 00011010 Data in the accumulator is logical AND with the data memory addressed by the register pair "R1,R0". ACC ACC "AND" M(R1,R0) Logical AND data memory with accumulator 00011101 Data in the data memory addressed by the register pair "R1,R0" is logical AND with the accumulator M(R1,R0) M(R1,R0) "AND" ACC 0000dddd The specified data is added to the accumulator. Carry is affected.
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CALL address Machine Code Description Operation Subroutine call 1111aaaa aaaaaaaa The program counter bits 0 1 1 are saved in the stack. The program counter is then loaded from the directly-specified address. Stack PC+2 PC address Clear carry flag 00101010 The carry flag is reset to 0 C0 Decimal Adjust accumulator 00110110 The accumulator value is adjusted to the BCD (Binary Code Decimal) code, if the contents of the accumulator is greater than 9 or C (Carry flag) is 1. If ACC>9 or CF=1 then ACC ACC+6, C 1 else ACC ACC, C C Decrement accumulator 00111111 Data in the accumulator is decremented by 1. Carry flag is not affected. ACC ACC 1 Decrement register 0001nnn1 Data in the working register "Rn" is decremented by 1. Carry flag is not affected. Rn Rn 1; Rn=R0, R1, R2, R3, R4, for n=0, 1, 2, 3, 4 Decrement data memory 00001101 Data in the data memory specified by the register pair "R1,R0" is decremented by 1. Carry flag is not affected. M(R1,R0) M(R1,R0) 1
CLC Machine Code Description Operation DAA Machine Code Description
Operation
DEC A Machine Code Description Operation DEC Rn Machine Code Description Operation DEC [R1R0] Machine Code Description Operation
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DEC [R3R2] Machine Code Description Operation DI Machine Code Description EI Machine Code Description HALT Machine Code Description Operation IN A,Pi Machine Code Description Operation INC A Machine Code Description Operation INC Rn Machine Code Description Operation INC [R1R0] Machine Code Description Operation Decrement data memory 00001111 Data in the data memory specified by the register pair "R3,R2" is decremented by 1. Carry flag is not affected. M(R3,R2) M(R3,R2)-1 Disable interrupt 00101101 Internal time-out interrupt and external interrupt are disabled. Enable interrupt 00101100 Internal time-out interrupt and external interrupt are enabled. Halt system clock 00110111 PC (PC)+1 Input port to accumulator 0 0 1 1 0 0 1 1 PS 0 0 1 1 0 1 0 0 PP The data on port "Pi" is transferred to the accumulator. ACC Pi; Pi=PS or PP Increment accumulator 00110001 Data in the accumulator is incremented by 1. Carry flag is not affected. ACC ACC+1 Increment register 0001nnn0 Data in the working register "Rn" is incremented by 1. Carry flag is not affected. Rn Rn+1; Rn=R0, R1, R2, R3, R4 for n=0, 1, 2, 3, 4 Increment data memory 00001100 Data in the data memory specified by the register pair "R1,R0" is incremented by 1. Carry flag is not affected. M(R1,R0) M(R1,R0)+1 00111110 Turn off system clock, and enter power down mode.
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INC [R3R2] Machine Code Description Operation JAn address Machine Code Description Increment data memory 00001110 Data memory specified by the register pair "R3,R2" is incremented by 1. Carry flag is not affected. M(R3,R2) M(R3,R2)+1 Jump if accumulator Bit n is set 100nnaaa aaaaaaaa Bits 0~10 of the program counter are replaced with the directly-specified address, bit 11 of the program counter and PA3 of the memory bank remain, if accumulator bit n is set to 1. PC (bit 0~10) address, if ACC bit n=1 (n=0,1,2,3,) PC PC+2, if ACC bit n=0 Jump if carry is set 11000aaa aaaaaaaa Bits 0~10 of the program counter are replaced with the directly-specified address, bit 11 of the program counter and PA3 of the memory bank remain, if C (Carry flag) is set to 1. PC (bit 0~10) address, if C=1 PC PC+2, if C=0 Direct Jump 1110aaaa aaaaaaaa Bits 0~11 of the program counter are replaced with the directly-specified address. PC address Jump if carry is not set 11001aaa aaaaaaaa Bits 0~10 of the program counter are replaced with the directly-specified address, bit 11 of the program counter and PA3 of the memory bank remain, if C (Carry flag) is set to 0. PC (bit 0~10) address, if C=0 PC PC+2, if C=1
Operation
JC address Machine Code Description
Operation
JMP address Machine Code Description Operation JNC address Machine Code Description
Operation
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JNZ A,address Machine Code Description Jump if accumulator is not 0 10111aaa aaaaaaaa Bits 0~10 of the program counter are replaced with the directly-specified address, bit 11 of the program counter and PA3 of the memory bank remain, if the accumulator is not 0. PC (bit 0~10) address, if ACC0 PC PC+2, if ACC=0 Jump if register is not 0 10100aaa 10101aaa 11011aaa a a a a a a a a R0 a a a a a a a a R1 a a a a a a a a R4
Operation
JNZ Rn,address Machine Code
Description
Bits 0~10 of the program counter are replaced with the directly-specified address, bit 11 of the program counter and PA3 of the memory bank remain, if the register is not 0. PC (bit 0~10) address, if Rn0; Rn=R0,R1,R4 PC PC+2, if Rn=0 Jump if time-out 11010aaa aaaaaaaa Bits 0~10 of the program counter are replaced with the directly-specified address, bit 11 of the program counter and PA3 of the memory bank remain, if the TF (Timer flag) is set to 1. PC (bit 0~10) address, if TF=1 PC PC+2, if TF=0 Jump if accumulator is 0 10110aaa aaaaaaaa Bits 0~10 of the program counter are replaced with the directly-specified address, bit 11 of the program counter and PA3 of the memory bank remain, if the accumulator is 0. PC (bit 0~10) address, if ACC=0 PC PC+2, if ACC0 Move register to accumulator 0010nnn1 Data in the working register "Rn" is moved to the accumulator. ACC Rn; Rn=R0, R1, R2, R3, R4, for n=0, 1, 2, 3, 4 Move timer to accumulator 00111011 The high nibble data of Timer counter is loaded to the accumulator. ACC TIMER (high nibble)
Operation
JTMR address Machine Code Description
Operation
JZ A,address Machine Code Description
Operation
MOV A,Rn Machine Code Description Operation MOV A,TMRH Machine Code Description Operation
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MOV A,TMRL Machine Code Description Operation MOV A,XH Machine Code Description Operation MOV A,[R1R0] Machine Code Description Operation MOV A,[R3R2] Machine Code Description Operation MOV R1R0,XXH Machine Code Description Move timer to accumulator 00111010 The low nibble data of Timer counter is loaded to the accumulator. ACC TIMER (low nibble) Move immediate data to accumulator 0111dddd The 4-bit data specified by code is loaded to the accumulator. ACC XH Move data memory to accumulator 00000100 Data in the data memory specified by the register pair "R1,R0" is moved to the accumulator. ACC M(R1,R0) Move data memory to accumulator 00000110 Data in the data memory specified by the register pair "R3,R2" is moved to the accumulator. ACC M(R3,R2) Move immediate data to R1 and R0 0101dddd 0000dddd The 8-bit data specified by code are loaded to the working registers R1 and R0, the high nibble of the data is loaded to R1, and the low nibble of the data is loaded to R0. R1 XH (high nibble) R0 XH (low nibble) Move immediate data to R3 and R2 0110dddd 0000dddd The 8-bit data specified by code are loaded to the working register R3 and R2, the high nibble of the data is loaded to R3, and the low nibble of the data is loaded to R2. R3 XH (high nibble) R2 XH (low nibble)
Operation
MOV R3R2,XXH Machine Code Description
Operation
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MOV R4,XH Machine Code Description Operation MOV Rn,A Machine Code Description Operation MOV TMRH,A Machine Code Description Operation MOV TMRL,A Machine Code Description Operation MOV [R1R0],A Machine Code Description Operation MOV [R3R2],A Machine Code Description Operation NOP Machine Code Description Move immediate data to R4 01000110 R4 XH Move accumulator to register 0010nnn0 Data in the accumulator is moved to the working register "Rn". Rn ACC; Rn=R0, R1, R2, R3, R4, for n=0, 1, 2, 3, 4 Move accumulator to timer 00111101 The contents of the accumulator is loaded to the high nibble of timer counter. TIMER (high nibble) ACC Move accumulator to timer 00111100 The contents of the accumulator is loaded to the low nibble of timer counter. TIMER (low nibble) ACC Move accumulator to data memory 00000101 Data in the accumulator is moved to the data memory specified by the register pair "R1,R0". M(R1,R0) ACC Move accumulator to data memory 00000111 Data in the accumulator is moved to the data memory specified by the register pair "R3,R2". M(R3,R2) ACC No operation 00111110 Do nothing, but one instruction cycle is delayed. 0000dddd The 4-bit data specified by code are loaded to the working register R4.
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OR A,XH Machine Code Description Operation OR A,[R1R0] Machine Code Description Operation OR [R1R0],A Machine Code Description Operation OUT PA,A Machine Code Description
Logical OR immediate data to accumulator 01000100 0000dddd Data in the accumulator is logical OR with the immediate data specified by code. ACC ACC "OR" XH Logical OR accumulator with data memory 00011100 Data in the accumulator is logical OR with the data memory addressed by the register pair "R1,R0". ACC ACC "OR" M(R1,R0) Logical OR data memory with accumulator 00011111 Data in the data memory addressed by the register pair "R1,R0" is logical OR with the accumulator. M(R1,R0) M(R1,R0) "OR" ACC Output accumulator data to port A 0 0 1 1 0 0 0 0 PA The data in the accumulator is transferred to the port-A and latched. Note: PA3 controls bit 13 of the program memory. Be careful about PA3 when port A is changed. PA ACC Read ROM code of current page to M(R1,R0) and ACC 01001110 The 8-bit ROM code (current page) addressed by ACC and R4 are moved to the data memory M(R1,R0) and accumulator. The high nibble of the ROM code is loaded to M(R1,R0) and the low nibble of the ROM code is loaded to the accumulator. The ROM code address are specified as shown below: Current page (R) ROM code address bit 12~8 ACC (R) ROM code address bit 7~4 R4 (R) ROM code address bit 3~0 M(R1R0) ROM code (high nibble) ACC ROM code (low nibble)
Operation READ MR0A Machine Code Description
Operation
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READ R4A Machine Code Description Read ROM code of current page to R4 and accumulator 01001100 The 8-bit ROM code (current page) addressed by ACC and M(R1,R0) are moved to the working register R4 and the accumulator. The high nibble of the ROM code is loaded to R4 and the low nibble of the ROM code is loaded to the accumulator. The ROM code address are specified below: Current page (R) ROM code address bit 12~8 ACC (R) ROM code address bit 7~4 M(R1,R0) (R) ROM code address bit 3~0 R4 ROM code (high nibble) ACC ROM code (low nibble) Read ROM Code of page F to M(R1,R0) and ACC 01001111 The 8-bit ROM code (page F) addressed by ACC and R4 are moved to the data memory M(R1,R0) and accumulator. The high nibble of the ROM code is loaded to M(R1,R0) and the low nibble of the ROM code is loaded to the accumulator. page F (R) ROM code address bit 12~8 are "PA3 1111" ACC (R) ROM code address bit 7~4 R4 (R) ROM code address bit 3~0 M(R1,R0) high nibble of ROM code (page F) ACC low nibble of ROM code (page F) Read ROM code of page F to R4 and accumulator 01001101 The 8-bit ROM code (page F) addressed by ACC and M(R1,R0) are moved to the working register R4 and the accumulator. The high nibble of the ROM code is loaded to R4 and the low nibble of the ROM code is loaded to the accumulator. page F (R) ROM code address bit 12~8 are "PA3 1111" ACC (R) ROM code address bit 7~4 M(R1,R0) (R) ROM code address bit 3~0 R4 high nibble of ROM code (page F) ACC low nibble of ROM code (page F) Return from subroutine or interrupt 00101110 The program counter bits 0~11 are restored from the stack. PC Stack
Operation
READF MR0A Machine Code Description
Operation
READF R4A Machine Code Description
Operation
RET Machine Code Description Operation
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RETI Machine Code Description Operation Return from interrupt subroutine 00101111 The program counter bits 0~11 are restored from the stack. The carry flag before entering interrupt service routine is restored. PC Stack C C (before interrupt service routine) Rotate accumulator left 00000001 The contents of the accumulator are rotated left 1 bit. Bit 3 is rotated to bit 0 and carry flag. An+1 An; An: accumulator bit n (n=0, 1, 2) A0 A3 C A3 Rotate accumulator left through carry 00000011 The contents of the accumulator are rotated left 1 bit. Bit 3 replaces the carry bit; the carry bit is rotated into the bit 0 position. An+1 An; An: Accumulator bit n (n=0, 1, 2) A0 C C A3 Rotate accumulator right 00000000 The contents of the accumulator are rotated right 1 bit. Bit 0 is rotated to bit 3 and carry flag. An An+1; An: Accumulator bit n (n=0, 1, 2) A3 A0 C A0 Rotate accumulator right through carry 00000010 The contents of the accumulator are rotated right 1 bit. Bit 0 replaces the carry bit; the carry bit is rotated into the bit 3 position. An An+1; An: Accumulator bit n (n=0,1,2) A3 C C A0
RL A Machine Code Description Operation
RLC A Machine Code Description Operation
RR A Machine Code Description Operation
RRC A Machine Code Description Operation
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SBC A,[R1R0] Machine Code Description Operation SOUND A Machine Code Description Subtract data memory contents and carry from ACC 00001010 The contents of the data memory addressed by the register pair "R1,R0" and carry are subtracted from the accumulator. Carry is affected. ACC ACC+M(R1,R0)+CF Active SOUND channel with accumulator 01001011 The activated sound begins playing in accordance with the contents of the accumulator when the specified sound channel is matched. Turn on sound repeat mode 01001001 The activated sound plays repeatedly. Turn off sound 01001010 The singing sound will terminate immediately. Turn on sound one mode 01001000 The activated sound plays only one time. Active SOUND Channel n 0000nnnn 01000101 The specified sound begins playing and overwriting the previous singing sound. (n=0~15) Set carry flag 00101011 The carry flag is set to1. C1 Subtract immediate data from accumulator 01000001 0000dddd The specified data is subtracted from the accumulator. Carry is affected. ACC ACC+XH+1
SOUND LOOP Machine Code Description SOUND OFF Machine Code Description SOUND ONE Machine Code Description SOUND n Machine Code Description
STC Machine Code Description Operation SUB A,XH Machine Code Description Operation
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SUB A,[R1R0] Machine Code Description Operation TIMER OFF Machine Code Description Subtract data memory contents from accumulator 00001011 The contents of the data memory addressed by the register pair "R1,R0" is subtracted from the accumulator. Carry is affected. ACC ACC+M(R1,R0)+1 Set timer to stop counting 00111001 The Timer stops counting, when the "TIMER OFF" instruction is executed. Set timer to start counting 00111000 The Timer starts counting, when the "TIMER ON" instruction is executed. Set immediate data to timer counter 01000111 TIMER XXH Logical XOR immediate data to accumulator 01000011 0000dddd Data in the accumulator is Exclusive-OR with the immediate data specified by code. ACC ACC "XOR" XH Logical XOR accumulator with data memory 00011011 Data in the accumulator is Exclusive-OR with the data memory addressed by the register pair "R1,R0". ACC ACC "XOR" M(R1,R0) Logical XOR data memory with accumulator 00011110 Data in the data memory addressed by the register pair "R1,R0" is logically Exclusive-OR with the accumulator. M(R1,R0) M(R1,R0) "XOR" ACC dddddddd The 8-bit data specified by code is loaded to the Timer counter.
TIMER ON Machine Code Description
TIMER XXH Machine Code Description Operation XOR A,XH Machine Code Description Operation XOR A,[R1R0] Machine Code Description Operation XOR [R1R0],A Machine Code Description Operation
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Holtek Semiconductor Inc. (Headquarters) No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C. Tel: 886-3-563-1999 Fax: 886-3-563-1189 Holtek Semiconductor Inc. (Taipei Office) 5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C. Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline) Holtek Microelectronics Enterprises Ltd. RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Copyright 1999 by HOL TEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
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